Devices incorporating wireless communications techniques are becoming increasingly prevalent in modern society. An inevitable result of this trend is that frequency spectrums are becoming more crowded and prone to interference. At the same time, consumers are becoming increasingly concerned about the privacy and security of wireless communications. Consequently, systems engineers designing a variety of wireless communications systems, including cellular and cordless telephones, to are increasingly turning to digital spread spectrum signaling methods to achieve greater security, higher signal-to-noise ratio, and more efficient bandwidth utilization than can be achieved by using conventional signaling methods, such as amplitude or frequency modulation without bandwidth spreading.
One popular spread spectrum signaling technique is known as frequency-hopping spread spectrum (xe2x80x9cFHSSxe2x80x9d). FHSS systems operate by rapidly changing their tuning frequency in a known pattern, referred to as the hop sequence. Multiple users each using different hop sequences can communicate simultaneously over independent communications channels on a single frequency range. However, because FHSS systems rely on the receiver and transmitter rapidly tuning to the desired frequency, many prior art designs require that significant microcontroller processing time be devoted to repeatedly programming a phase-locked loop to tune new channels.
Consequently, one object of the present invention is to provide a hardware-implemented phase-locked loop controller for programming a phase-locked loop, thereby allowing the general purpose microcontroller to devote its processing power to implementing more advanced functionality.
When designing wireless communications systems using portable units, the battery life of the portable unit is a key design parameter. Some prior art FHSS portable units significantly extend their battery life by periodically entering a xe2x80x9csleepxe2x80x9d mode, in which many system components are de-powered. However, the portable unit""s responsiveness is often significantly compromised, because upon xe2x80x9cawakeningxe2x80x9d from sleep mode the unit must perform a complete resynchronization procedure before to communication with the base unit can resume. Other systems may continuously maintain synchronization albeit at the expense of decreased battery life. It is therefore an object of this invention to provide a phase-locked loop (PLL) controller which allows a transceiver to enter a very low power sleep mode, and yet resume communications immediately upon awakening.
Another aspect of FHSS systems which is especially advantageous is the ability to avoid interference on a particular frequency channel by dynamically changing the channels in the hop sequence, substituting a new xe2x80x9cclearxe2x80x9d channel frequency for an detected xe2x80x9cbadxe2x80x9d channel frequency. Therefore, another object of the present invention is to allow simple implementation of dynamic channel allocation.
Phase-locked loop circuits may require specific configuration programming prior to use. Designers may also wish to allow for specific control of the phase-locked loop during diagnostic or other modes of operation. Consequently, it is an object of the present invention to allow for an override of the default hardware-controlled phase-locked loop programming sequence.
Furthermore, in designing a digital wireless communications system, it is often desirable to allow a portable unit to communicate to any one of a plurality of base units spread throughout a region, such as in the case of the implementation of a cellular telephone system. This configuration allows a user of the portable unit to communicate throughout a wide area, while requiring only enough transmit power to reach the nearest base unit. Consequently, portable unit battery life is improved, and interference with other nearby users of the frequency band is decreased. However, to implement such functionality in a FHSS system, transceivers in the portable and base units must have synchronized hop sequences such that a portable unit will be able to communicate to any base unit which is loaded with the same hop sequence. It is therefore an object of this invention to provide a hardware-implemented PLL controller with hop synchronization ports which may be used to synchronize the hop sequences of multiple units in a system.
These and other objects of the present invention will become apparent in light of the present specification and drawing.
In accordance with the invention, a hardware implemented phase-locked loop controller is provided which utilizes an indirect addressing scheme to access PLL data for repeated programming of a phase-locked loop at a fixed rate. The invention consists of a hop counter, a pattern register, a PLL data table, and a data control circuit.
The hop counter periodically increments its state between zero and a specified maximum value. Upon reaching the maximum value, the counter state is reset back to zero. In accordance with one aspect of the invention, the hop counter may maintain hop sequence synchronization while a transceiver is placed in a low-power sleep mode, thereby allowing instantaneous resumption of communications upon awakening. In accordance with another aspect of the invention, the hop counter may provide for synchronization between multiple transceivers in a communications system. The hop counter can generate a sync signal upon reaching its maximum state, which can be transmitted to additional transceivers in the system to force the simultaneous reset of additional hop counters.
The pattern register is an addressable memory area addressed by the hop counter, which outputs channel numbers comprising the hop sequence. In accordance with one aspect of the invention, the pattern register may include an input whereby an external circuit can write new values to locations in the pattern register, thereby enabling the implementation of dynamic channel allocation techniques without interrupting communications.
The PLL data table converts the channel number to which the phase-locked loop is to be tuned, into the control words which tune the phase-locked loop to the desired frequency. The specific control words may vary according to the design of the phase-locked loop circuit.
The data control circuit provides a programming interface to send the PLL data table output to the phase-locked loop device. For example, many phase-locked loop devices are programmed via a serial programming interface, in which case the data control circuit may include a parallel to serial converter, and may further synthesize clock and frame signals as required by the PLL programming model. Optionally, the data control circuit may also provide signals to control RF circuit functionality, as is desired to effectuate a proper channel change. Finally, the data control circuit may include provisions for an overriding input, through which an external circuit can control the PLL programming regardless of the PLL data table output.